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holtek 32-bit microcontroller with arm ? cortex?-m3 core HT32F1755/ht32f1765/ht32f2755 datasheet revision: v1.00 date: ???? st 1?? ?01? ????st 1?? ?01?
rev. 1.00 ? of 45 ????st 1?? ?01? ??-bit ?rm cortex?-m? mcu ht??f1755/ht??f1765/ht??f?755 table of contents table of contents 1 general description ................................................................................................ 6 2 features ................................................................................................................... 7 core ....................................................................................................................................... 7 on-chip memory .................................................................................................................... 7 flash memory controller ....................................................................................................... 8 reset control unit ................................................................................................................. 8 clock control unit .................................................................................................................. 8 power mana?ement ............................................................................................................... 9 ?nalo? to di?ital converter .................................................................................................... 9 analog operational amplifer/comparator ............................................................................. 9 i/o ports ............................................................................................................................... 10 pwm generation and capt? re timers C gptm .................................................................. 10 motor control timer C mctm .............................................................................................. 11 basic f? nction timer C bftm ............................................................................................. 11 watchdo ? timer ................................................................................................................... 1? real time clock ................................................................................................................... 1? inter-inte?rated circ?it C i ? c ................................................................................................ 1? serial peripheral interface C spi ......................................................................................... 1? universal synchrono?s ?synchrono? s receiver transmitter C us? rt .............................. 14 smart card interface C sci ................................................................................................. 14 peripheral direct memory ?ccess C pdm? ......................................................................... 15 universal serial b?s device controller C usb .................................................................... 15 cmos sensor interface C csif (ht??f?755 only) ............................................................ 16 deb?? s?pport ..................................................................................................................... 16 packa? e and operation temperat?re .................................................................................. 16 3 overview ................................................................................................................ 17 device information ............................................................................................................... 17 block dia?ram ..................................................................................................................... 18 memory map ........................................................................................................................ 19 clock str?ct?re .................................................................................................................... ?0 pin ?ssi?nment .................................................................................................................... ?1
rev. 1.00 ? of 45 ????st 1?? ?01? ??-bit ?rm cortex?-m? mcu ht??f1755/ht??f1765/ht??f?755 table of contents table of contents 4 electrical characteristics ..................................................................................... 28 ?bsol?te maxim?m ratin?s ................................................................................................. ?8 recommended dc characteristics ..................................................................................... ?8 on-chip ldo volta ?e re??lator characteristics ................................................................. ?8 power cons?mption ............................................................................................................ ?9 reset and s?pply monitor characteristics ........................................................................... ?9 external clock characteristics ............................................................................................. ?0 internal clock characteristics .............................................................................................. ?1 pll characteristics .............................................................................................................. ?1 memory characteristics ....................................................................................................... ?1 i/o port characteristics ........................................................................................................ ?? ?dc characteristics ............................................................................................................ ?? operation amplifer/comparator characteristics ................................................................. ?5 gptm/mctm characteristics .............................................................................................. ?5 i ? c characteristics ............................................................................................................... ?6 spi characteristics .............................................................................................................. ?7 csif characteristics ............................................................................................................ ?8 usb characteristics ............................................................................................................. ?9 5 package information ............................................................................................ 41 48-pin lqfp (7mm7mm) o ?tline dimensions ................................................................... 41 64-pin lqfp (7mm7mm) o ?tline dimensions ................................................................... 4? 100-pin lqfp (14mm14mm) o ?tline dimensions ............................................................. 44
rev. 1.00 4 of 45 ????st 1?? ?01? ??-bit ?rm cortex?-m? mcu ht??f1755/ht??f1765/ht??f?755 list of tables list of tables table 1. ht ??f1755/1765/?755 series feat?res and peripheral list ................................................... 17 table ?. ht??f1755/1765/?755 pin descriptions ................................................................................. ?4 table ?. ?bsol?te maxim?m ratin?s ...................................................................................................... ?8 table 4. recommended dc operatin ? conditions ................................................................................ ?8 table 5. ldo characteristics ................................................................................................................. ?8 table 6. power cons ?mption characteristics ........................................................................................ ?9 table 7. lvd/bod characteristics ......................................................................................................... ?9 table 8. hi ?h speed external clock (hse) characteristics ................................................................... ?0 table 9. low speed external clock (lse) characteristics .................................................................... ?0 table 10. hi ?h speed internal clock (hsi) characteristics ................................................................... ?1 table 11. low speed internal clock (lsi) characteristics ..................................................................... ?1 table 1 ? . pll characteristics ................................................................................................................ ?1 table 1 ?. flash memory characteristics ................................................................................................ ?1 table 14. i/o port characteristics .......................................................................................................... ?? table 15. ?dc characteristics ............................................................................................................... ?? table 16. op ? /cmp characteristics ...................................................................................................... ?5 table 17. gptm/mctm characteristics ................................................................................................ ?5 table 18. i ? c characteristics .................................................................................................................. ?6 table 19. spi characteristics ................................................................................................................. ?7 table ?0. csif characteristics .............................................................................................................. ?8 table ?1. usb dc electrical characteristics ......................................................................................... ?9 table ??. usb ?c electrical characteristics .......................................................................................... 40
rev. 1.00 5 of 45 ????st 1?? ?01? ??-bit ?rm cortex?-m? mcu ht??f1755/ht??f1765/ht??f?755 list of tables list of figures list of figures fi??re 1. ht??f1755/1765/?755 block dia?ram .................................................................................. 18 fi??re ?. ht??f1755/1765/?755 memory map ..................................................................................... 19 fi??re ?. ht??f1755/1765/?755 clock str?ct?re ................................................................................. ?0 fi??re 4. ht??f1755/1765/? 755 48-lqfp pin ?ssi?nment ................................................................. ?1 fi??re 5. ht??f1755/1765/? 755 64-lqfp pin ?ssi?nment ................................................................. ?? fi??re 6. ht??f1755/1765/? 755 100-lqfp pin ?ssi?nment ............................................................... ?? fi??re 7. ?dc samplin? network model ............................................................................................... ?4 fi??re 8. i ? c timin ? dia?rams ............................................................................................................... ?6 fi?? re 9. spi timin? dia?rams C spi master mode .............................................................................. ?7 fi?? re 10. spi timin? dia?rams C spi slave mode and cph?=1 ........................................................ ?8 fi?? re 11. usb si? nal rise time and fall time and cross-point volta?e (v crs ) defnition ................... 40
rev. 1.00 6 of 45 ????st 1?? ?01? ??-bit ?rm cortex?-m? mcu ht??f1755/ht??f1765/ht??f?755 general description 1 general description the holtek HT32F1755/1765/2755 devices are high performance and low power consumption 32-bit microcontrollers based around an arm ? cortex?-m3 processor core. the cortex?-m3 is a next-generation processor core which is tightly coupled with nested vectored interrupt controller (nvic), systick timer, and including advanced debug support. the HT32F1755/1765/2755 devices operate at a frequency of up to 72mhz with a flash accelerator to obtain maximum effciency. it provides 128kb of embedded flash memory for code/data storage and up to 64kb of embedded sram memory for system operation and application program usage. a variety of peripherals, such as adc, i 2 c, usart, spi, pdma, gptm, mctm, sci, csif, usb2.0 fs, swj-dp (serial wire and jtag debug port), etc., are also implemented in the device series. several power saving modes provide the flexibility for maximum optimisation between wakeup latency and power consumption, an especially important consideration in low power applications. the above features ensure that the HT32F1755/1765/2755 devices are suitable for use in a wide range of applications, especially in areas such as white goods application control, power monitors, alarm systems, consumer products, handheld equipment, data logging applications, motor control, fngerprint recognition and so on.
rev. 1.00 7 of 45 ????st 1?? ?01? ??-bit ?rm cortex?-m? mcu ht??f1755/ht??f1765/ht??f?755 general description features 2 features core ? 32-bit arm ? cortex?-m3 processor core ? up to 72mhz operation frequency ? 1.25 dmips/mhz (dhrystone 2.1) ? single-cycle multiplication and hardware division ? integrated nested vectored interrupt controller (nvic) ? 24-bit systick timer the cortex?-m3 processor is a general-purpose 32-bit processor core especially suitable for products requiring high performance and low power consumption microcontrollers. it offers many new features such as a thumb-2 instruction set, hardware divider, low latency interrupt respond time, atomic bit-banding access and multiple buses for simultaneous accesses. the cortex?-m3 processor is based on the armv7 architecture and supports both thumb and thumb-2 instruction sets. on-chip memory ? 128 kb on-chip flash memory for instruction/data and options storage ? up to 64 kb on-chip sram ? supports multiple boot modes the arm ? cortex?-m3 processor is structured using a harvard architecture which uses separate busses to fetch instructions and load/store data. the instruction code and data are both located in the same memory address space but in different address ranges. the maximum address range of the cortex?-m3 is 4gb due to its 32-bit bus address width. additionally , a pre-defned memory map is provided by the cortex?-m3 processor to reduce the software complexity of repeated implementation for different device vend ors . however, some regions are used by the arm ? cortex?-m3 system peripherals. r efer to the arm ? cortex?-m3 technical reference manual for more information. the figure 2. shows the memory map of the HT32F1755/1765/2755 series of devices , including code, sram, peripheral, and other pre-defned regions.
rev. 1.00 8 of 45 ????st 1?? ?01? ??-bit ?rm cortex?-m? mcu ht??f1755/ht??f1765/ht??f?755 features flash memory controller ? flash accelerator for maximum effciency ? 32-bit word programming with in system programming interface (isp) and in application programming (iap) ? flash protection capability to prevent illegal access the flash memory controller , fmc , provides all the necessary functions and pre-fetch buffer for the embedded on-chip flash memory. since the access speed of the flash memory is slower than the cpu, a wide access interface with a pre-fetch buffer is provided for the flash memory in order to reduce the cpu wait ing time which will cause cpu instruction execution delays . flash memory word program/page erase functions are also provided . reset control unit ? supply supervisor: power -on reset C por brown-out detector C bod programmable low voltage detector C lvd the reset control unit (rstcu) has three kinds of reset, the power on reset, system reset and an apb unit reset. the power on reset, known as a cold reset, resets the full system during power up. a system reset resets the processor core and peripheral ip components with the exception of the swj-dp controller. the resets can be triggered by an external signal, internal events and the reset generators. clock control unit ? external 4 to 16mhz crystal oscillator ? external 32,768hz crystal oscillator ? internal 8mhz rc oscillator trimmed to 2% accuracy at 3.3v operating voltage and 25c operating temperature ? internal 32khz rc oscillator ? integrated system clock pll ? independent clock gating bits for peripheral clock sources the clock control unit, ckcu, provides a range of oscillator and clock functions. these include a high speed internal rc oscillator (hsi), a high speed external crystal oscillator (hse), a low speed internal rc oscillator (lsi), a low speed external crystal oscillator (lse), a phase lock loop (pll), a hse clock monitor, clock prescalers, clock multiplexers and clock gating circuitry. the clocks of the ahb, apb and cortex tm -m3 are derived from the system clock (ck_sys) which can come from the hsi, hse or pll. the watchdog timer and real time clock (rtc) use either the lsi or lse as their clock source. the maximum operating frequency of the system core clock (ck_ahb) can be up to 72mhz.
rev. 1.00 9 of 45 ????st 1?? ?01? ??-bit ?rm cortex?-m? mcu ht??f1755/ht??f1765/ht??f?755 features features power management ? single 3.3v power supply: 2.7v to 3.6v ? integrated 1.8v ldo regulator for core and peripheral power supply ? v b at battery power supply for rtc and backup registers ? three power domains: 3.3v, 1.8v and backup ? four power saving modes: sleep, deep-sleep1, deep-sleep2, power-down the power consumption can be regarded as one of the most important issues for many embedded system applications. accordingly the power control unit, pwrcu, in these devices provides many types of power saving modes such as sleep, deep-sleep1, deep-sleep2 and power-down mode. these operating modes reduce the power consumption and allow the application to achieve the best trade-off between the conficting demands of cpu operating time, speed and power consumption. analog to digital converter ? 12-bit sar adc engine ? up to 1msps conversion rate C 1s at 56mhz, 1.17s at 72mhz ? 8 external analog input channels ? supply voltage range: 2.7v ~ 3.6v ? conversion range: v ref+ ~ v ref- a 12-bit multi-channel adc is integrated in the device. there are a total of 10 multiplexed channels , which include 8 external channels on which the external analog signals can be measured , and 2 internal channels . if the input voltage is required to remain within a specific threshold window, an analog watchdog function will monitor and detect these signals. an interrupt will then be generated to inform the device that the input voltage is not within the preset threshold levels. there are three conversion modes to convert an analog signal to digital data. the adc can be operated in one shot, continuous and discontinuous conversion mode s . analog operational amplifer/comparator ? two operational amplifers or comparator functions which are software confgurable ? supply voltage range: 2.7v ~ 3.6v two operational amplifers/comparators (opa/cmp) are implemented within the devices. they can be confgured either as operational amplifers or as analog comparators. when confgured as comparators, they are capable of generating interrupts to the nvic.
rev. 1.00 10 of 45 ????st 1?? ?01? ??-bit ?rm cortex?-m? mcu ht??f1755/ht??f1765/ht??f?755 features i/o ports ? up to 80 gpios ? port a, b, c, d, e are mapped as 16 external interrupts C exti ? almost all i/o pins are 5v-tolerant except for pins shared with analog inputs there are up to 80 general purpose i/o pins , (gpio), named pa0 ~ pa15 to pe0 ~ pe15 for the implementation of logic input/output functions. each of the gpio ports has a series of related control and confguration registers to maximise fexibility and to meet the requirements of a wide range of applications . the gpio ports are pin-shared with other alternative functions to obtain maximum functional flexibility on the package pins. the gpio pins can be used as alternative functional pins by confguring the corresponding registers regardless of the input or output pins. the external interrupts on the gpio pins of the device have related control and configuration registers in the external interrupt control unit, exti. pwm generation and capture timers C gptm ? two 16-bit general-purpose timers C gptm ? up to 4-channel pwm compare output or input capture function for each gptm ? external trigger input the general-purpose timers, known as gptm0 and gptm1, consist of one 16-bit up/down-counter, four 16-bit capture/compare registers (ccrs), one 16-bit counter-reload register (crr) and several control/status registers. they can be used for a variety of purposes including general time measurement, input signal pulse width measurement, output waveform generation such as single pulse generation, or pwm output generation. the gptm supports an encoder interface using a decoder with two inputs.
rev. 1.00 11 of 45 ????st 1?? ?01? ??-bit ?rm cortex?-m? mcu ht??f1755/ht??f1765/ht??f?755 features features motor control timer C mctm ? single 16-bit up, down, up/down auto-reload counter ? 16-bit programmable prescaler allowing dividing the counter clock frequency by any factor between 1 and 65536 ? input capture function ? compare match output ? pwm waveform generation with edge and centre-aligned modes ? single pulse mode output ? complementary outputs with programmable dead-time insertion ? encoder interface controller with two inputs using quadrature decoder ? support 3-phase motor control and hall sensor interface ? brake input to force the timers output signals into a reset or fxed condition the motor control timer consists of a single 16-bit up/down counter, four 16-bit ccrs (capture/compare registers), single one 16-bit counter-reload register (crr), single 8-bit repetition counter and several control/status registers. it can be used for a variety of purposes including measuring the pulse widths of input signals or generating output waveforms such as compare match outputs, pwm outputs or complementary pwm outputs with dead-time insertion. the mctm supports an encoder interface controller to an incremental encoder with two inputs. the mctm is capable of offering full functional support for motor control, hall sensor interfacing and brake input. basic function timer C bftm ? two 32-bit compare/match count-up counters C no i/o control features ? one shot mode C counting stops after a match condition ? repetitive mode C restart counter after a match condition the basic function timer is a simple count-up 32-bit counter designed to measure time intervals and generate a one shot or repetitive interrupts. the bftm operates in two functional modes, repetitive or one shot mode. in the repetitive mode the bftm restarts the counter when a compare match event occurs. the bftm also supports a one shot mode which forces the counter to stop counting when a compare match event occurs.
rev. 1.00 1? of 45 ????st 1?? ?01? ??-bit ?rm cortex?-m? mcu ht??f1755/ht??f1765/ht??f?755 features watchdog timer ? 12-bit down counter with 3-bit prescaler ? interrupt or reset event for the system ? programmable watchdog timer window function ? registers write protection function the watchdog timer is a hardware timing circuit that can be used to detect system failures due to software malfunctions. it includes a 12-bit count-down counter, a prescaler, a wdt counter value register, a wdt delta value register, interrupt related circuits, wdt operation control circuitry and a wdt protection mechanism. the watchdog timer can be operated in an interrupt mode or a reset mode. the watchdog timer will generate an interrupt or a reset when the counter counts down and reaches a zero value. if the software does not reload the counter value before a watchdog timer underfow occurs, an interrupt or a reset will be generated when the counter underfows. in addition, an interrupt or reset is also generated if the software reloads the counter when the counter value is greater than or equal to the wdt delta value. this means the counter must be reloaded within a limited timing window using a specific method. the watchdog timer counter can be stopped while the processor is in the debug mode. there is a register write protect function which can be enabled to prevent it from changing the watchdog timer confguration unexpectedly. real time clock ? 32-bit up-counter with a programmable prescaler ? alarm function ? interrupt and wake-up event the real time clock, rtc, circuitry includes the apb interface, a 32-bit count-up counter, a control register, a prescaler, a compare register and a status register. most of the rtc circuits are located in the backup domain except for the apb interface. the apb interface is located in the v dd18 power domain. therefore, it is necessary to be isolated from the iso signal that comes from the power control unit when the v dd18 power domain is powered off, that is when the device enters the power-down mode. the rtc counter is used as a wakeup timer to generate a system resume signal from the power-down mode.
rev. 1.00 1? of 45 ????st 1?? ?01? ??-bit ?rm cortex?-m? mcu ht??f1755/ht??f1765/ht??f?755 features features inter-integrated circuit C i 2 c ? support both master and slave mode with a frequency of up to 1mhz ? provide an arbitration function and clock synchronization ? support s 7-bit and 10-bit addressing mode and general call addressing ? support s slave multi-addressing mode with maskable address the i 2 c module is an internal circuit allowing communication with an external i 2 c interface which is an industry standard two line serial interface used for connection to external hardware. these two serial lines are known as a serial data line, sda, and a serial clock line, scl. the i 2 c module provides three data transfer rates: (1). 100khz in the standard mode, (2). 400khz in the fast mode and, (3). 1mhz in the fast mode plus. the scl period generation register is used to setup different kinds of duty cycle implementation for the scl pulse. the sda line which is connected directly to the i 2 c bus is a bi-directional data line between the master and slave devices and is used for data transmission and reception. the i 2 c module also has an arbitration detect function and clock synchronization to prevent situations where more than one master attempts to transmit data to the i 2 c bus at the same time. serial peripheral interface C spi ? supports both master and slave mode ? frequency of up to 36mhz for master mode and 18mhz for slave mode ? fifo depth: 8 levels ? multi-master and multi-slave operation the serial peripheral interface, spi, provides an spi protocol data transmit and receive function in both master and slave mode. the spi interface uses 4 pins, which are the serial data input and output lines miso and mosi, the clock line, sck, and the slave select line, sel. one spi device acts as a master device which controls the data fow using the sel and sck signals to indicate the start of data communication and the data sampling rate. to receive a data byte, the streamed data bits are latched on a specifc clock edge and stored in the data register or in the rx fifo. data transmission is carried in a similar way but with a reverse sequence. the mode fault detection provides a capability for multi-master applications.
rev. 1.00 14 of 45 ????st 1?? ?01? ??-bit ?rm cortex?-m? mcu ht??f1755/ht??f1765/ht??f?755 features universal synchronous asynchronous receiver transmitter C usart ? operating frequency up to 4.5mhz ? supports both asynchronous and clocked synchronous serial communication modes ? irda sir encoder and decoder ? rs485 mode with output enable control ? full modem function for usart0 ? auto hardware fow control mode C rts, cts ? fifo depth: 169 bits for both receiver and transmitter the universal synchronous asynchronous receiver transceiver, usart, provides a flexible full duplex data exchange using synchronous or asynchronous transfer. the usart is used to translate data between parallel and serial interfaces, and is also commonly used for rs232 standard communication. the usart peripheral function supports fve types of interrupt including line status interrupt, transmitter fifo empty interrupt, receiver threshold level reaching interrupt, time out interrupt and modem status interrupt. the usart module includes a 16-byte transmitter fifo (tx_fifo) and a 16-byte receiver fifo (rx_fifo). the software can detect a usart error status by reading the line status register, lsr. the status includes the type and the condition of transfer operations as well as several error conditions resulting from parity, overrun, framing and break events. the usart includes a programmable baud rate generator which is capable of dividing the ck_ahb to produce a clock for the usart transmitter and receiver. smart card interface C sci ? support iso 7816-3 standard ? character mode ? single transmit buffer and single receive buffer ? 11-bit etu (elementary time unit) counter ? 9-bit guard time counter ? 24-bit general purpose waiting time counter ? parity generation and checking ? automatic character retry on parity error detection in transmission and reception modes the smart card interface is compatible with the iso 7816-3 standard. this interface includes card insertion/removal detection, sci data transfer control logic and data buffers, internal timer counters and corresponding control logic circuits to perform all the necessary smart card operations. the smart card interface acts as a smart card reader to facilitate communication with the external smart card. the overall functions of the smart card interface are controlled by a series of registers including control and status registers together with several corresponding interrupts which are generated to get the attention of the microcontroller for sci transfer status.
rev. 1.00 15 of 45 ????st 1?? ?01? ??-bit ?rm cortex?-m? mcu ht??f1755/ht??f1765/ht??f?755 features features peripheral direct memory access C pdma ? 12 channels with trigger source grouping ? supports single and block transfer mode ? 8/16/32-bit width data transfer ? supports address increment, decrement or fxed mode ? 4-level programmable channel priority ? auto reload mode ? supports trigger source: csif, adc, spi, usart, i 2 c, gptm, mctm, sci and software the peripheral direct memory access controller, pdma, moves data between the peripherals (usart, spi, adc, gptm, mctm, csif, i 2 c and sci, cpu for software mode) and the system memory on the ahb bus. each pdma channel has a source address, destination address, block length and transfer count. the pdma can exclude the cpu intervention and avoid interrupt service routine execution. it improves system performance as the software does not need to join each data movement operation. universal serial bus device controller C usb ? complies with usb 2.0 full-speed (12mbps) specifcation ? on-chip usb full-speed transceiver ? 1 control endpoint (ep0) for control transfer ? 3 single-buffered endpoints for bulk and interrupt transfer ? 4 double-buffered endpoints for bulk, interrupt and isochronous transfer ? 1024 bytes ep-sram used as the endpoint data buffers the usb device controller is compliant with usb 2.0 full-speed specifcation. there is one control endpoint known as endpoint 0 and seven confgurable endpoints. a 1024-byte sram is used as the endpoint buffers. each endpoint buffer size is programmable using corresponding registers, which provides maximum fexibility for various applications. the integrated usb full-speed transceiver helps to minimise the overall system complexity and cost. the usb functional block also contains the resume and suspend features to meet the requirements of low-power consumption.
rev. 1.00 16 of 45 ????st 1?? ?01? ??-bit ?rm cortex?-m? mcu ht??f1755/ht??f1765/ht??f?755 features cmos sensor interface C csif (ht32f2755 only) ? up to 20482048 input resolution ? supports 8-bit yuv422 and raw rgb formats ? up to 24mhz input pixel clock frequency ? multi vsync and hsync settings for image capture ? hardware window capture function ? fractional hardware sub-sample function ? dual fifos each with a capacity of 832 bits which can be read by the pdma or cpu the cmos sensor interface, otherwise known as the csif, provides an interface for image capture from cmos sensors. the device can be connected to the cmos sensor directly using its cmos sensor interface. the csif supports both vertical sync and horizontal sync modes for image capture implementation. the csif consists of window capture and sub-sampling functions together with dual fifos, each with a capacity of 832 bits, to store data which can be moved to the internal sram via the peripheral direct memory access circuitry, pdma. the csif does not support image data conversion or decode but rather transfers the image data received from the cmos sensor to the internal sram transparently. debug support ? serial wire or jtag debug port swj-dp ? 6 instruction comparators and 2 literal comparators for hardware breakpoint or code/literal patch ? 4 comparators for hardware watchpoints ? 1-bit asynchronous trace C traceswo package and operation temperature ? 48/64/100-pin lqfp packages ? operation temperature range: -40 c to +85 c
rev. 1.00 17 of 45 ????st 1?? ?01? ??-bit ?rm cortex?-m? mcu ht??f1755/ht??f1765/ht??f?755 features overview 3 overview device information table 1. HT32F1755/1765/2755 series features and peripheral list peripherals HT32F1755 ht32f1765 ht32f2755 main flash (kb) 1?7 1?7 1?7 option bytes flash (kb) 1 1 1 sr?m (kb) ?? 64 64 timers mctm 1 gptm ? bftm ? rtc 1 wdt 1 comm?nication csif 1 usb 1 sci 1 us? rt ? spi ? i ? c ? gpio up to 80 exti 16 1?-bit ?dc n?mber of channels 1 8 channels op ?/comparator ? cpu freq?ency up to 7?mhz operatin? volta?e ?.7v ~ ?.6v operatin? temperat?re -40 ~ +85 packa?e 48/64/100-pin lqfp
rev. 1.00 18 of 45 ????st 1?? ?01? ??-bit ?rm cortex?-m? mcu ht??f1755/ht??f1765/ht??f?755 overview block diagram tpiu swj - dp apb1 apb 0 ahb to apb bridge ahb peripherals flash memory icode dcode cortex tm -m 3 processor f max : 72 mhz system ahb to apb bridge nvic sram controller fmc control registers ckcu /rstcu control registers pdma control registers pdma 12 channels pdma request interrupt request usart0 spi0 afio exti spi 1 wdt spi0_mosi, spi0_miso, spi0_sck, spi0_sel powered by v ldoin pll f max : 144 mhz por 1.8 v gt0_ ch0~ gt0_ ch3, gt0_ eti boot 0 boot 1 clock and reset control bod lvd xtalin xtalout hsi 8 mhz hse 4 ~ 16 mhz power control bus matrix af af af af af af af af ldo 1. 8 v powered by v dd18 csif control /data registers jtrst, jtdi , jtdo, jtck_swclk , jtms _swdio pa [15:0] i 2c 0_sda, i 2c 0_scl af usart1 usb device power supply: bus: control signal: alternate function : af powered by v dd18 spi 1 _mosi, spi 1 _miso, spi 1 _sck, spi 1 _sel af af usbdp usbdm csif _ vsync , csif _hsync , csif _ mck , csif _pck, csif _ d [ 7: 0] af flash memory interface ur0_tx, ur0_rx, ur0_dcd, ur0_dsr, ur0_dtr, ur0_ri ur0_rts/txe ur0_cts/sck ur1_ tx , ur1_ rx , ur1_ rts/ txe , ur1_ cts/ sck mt_ch0~ mt_ch3 , mt_ch0n~ mt_ch2n , mt_ch3 , mt_eti , mt_brk . af xtal32kin xtal 32kout af porb v bak 3.3 v lsi 32 khz lse 32, 768 hz breg backup domain v bak v bak pwrsw rtc pwrcu nrst rtcout wakeup af af gpiob gpioc gpiod pb [15:0] pc [15:0] pd [15:0] gptm 0 ~ 1 sram analog opa/cmp powered by v dda vdda cn0, cp0 aout0 cn1, cp1 aout1 opa /cmp adc_in0 : adc_in7 af af gpioa i 2 c 0 ~ 1 adc 12 -bit sar adc traceswo mctm pe [15:0] gpioe bftm 0 ~ 1 sci af mpu sci_clk, sci_dio , sci_det vssa vbat vldoin gt1_ ch0~ gt1_ ch3, gt1_ eti i 2c 1_sda, i 2c 1_scl vldoin vldoout vdd33 _1~4 vss33 _ 1~4 vref+, vref- vssldo v dd 18 note: the ?hb peripheral f?nction? csif ? is only available in the ht??f?755 device. figure 1. HT32F1755/1765/2755 block diagram
rev. 1.00 19 of 45 ????st 1?? ?01? ??-bit ?rm cortex?-m? mcu ht??f1755/ht??f1765/ht??f?755 overview overview memory map 1?8 kb on-chip flash 0x0000_0000 reserved 0x000?_0000 boot loader 0x1f00_0000 reserved 0x1f00_0800 option bytes alias 0x1ff0_0000 1?8 kbytes ? kbytes 1 kbytes reserved 0x1ff0_0400 code sr?m peripheral 0x?000_0000 reserved 0x?001_0000 sr?m bit band alias 0x??00_0000 reserved 0x???0_0000 64 kbytes (ht??f1765/ ht??f?755) ? mbytes ?pb peripherals 0x4000_0000 ?hb peripherals 0x4008_0000 reserved 0x4010_0000 ?pb/?hb bit band alias 0x4?00_0000 reserved 0x4400_0000 private peripheral b?s 0xe000 _0000 reserved 0xe010_0000 0xffff_ffff 51? kbytes 51? kbytes ?? mbytes us?rt0 0x4000_0000 reserved 0x4000_1000 spi0 0x4000_4000 reserved 0x4000_5000 ?dc 0x4001_0000 0x4001_1000 reserved op?/cmp 0x4001_8000 reserved 0x4001_9000 gpio? 0x4001_?000 gpiob 0x4001_b000 gpioc 0x4001_c000 gpiod 0x4001_d000 gpioe 0x4001_e000 0x4001_f000 reserved ?fio 0x400?_?000 reserved 0x400?_?000 exti 0x400?_4000 reserved 0x400?_5000 mctm 0x400?_c000 0x400?_d000 reserved us?rt1 0x4004_0000 reserved 0x4004_1000 sci 0x4004_?000 reserved 0x4004_5000 spi1 0x4004_4000 i?c0 0x4004_8000 reserved 0x4004_?000 i?c1 0x4004_9000 reserved 0x4004_f000 usb 0x4004_e000 reserved 0x4006_9000 wdt 0x4006_8000 reserved 0x4006_b000 rtc/pwrcu 0x4006_?000 gptm0 0x4006_e000 reserved 0x4007_0000 gptm1 0x4006_f000 bftm0 0x4007_6000 reserved 0x4007_8000 bftm1 0x4007_7000 ?pb0 ?pb1 fmc 0x4008_0000 reserved 0x4008_?000 ckcu/rstcu 0x4008_8000 reserved 0x4008_?000 pdm? 0x4009_0000 reserved 0x4009_?000 csif 0x400c_ c000 reserved 0x400c_e 000 0x400f_ffff ?hb ?? kb on-chip sr?m ?? kb on-chip sr?m ?? kbytes (ht??f1755) figure 2. HT32F1755/1765/2755 memory map
rev. 1.00 ?0 of 45 ????st 1?? ?01? ??-bit ?rm cortex?-m? mcu ht??f1755/ht??f1765/ht??f?755 overview clock structure 4-16 mhz hse xt?l 8 mhz hsi rc ?? khz lsi rc le?end: hse = hi?h speed external clock hsi = hi?h speed internal clock lse = low speed external clock lsi = low speed internal clock ??.768 khz lse osc wdtsrc pllsrc ?hb prescaler 1???4?8 fclk ( free r?nnin? clock) hclkd ( to dm?) stclk (to systick) ?dc prescaler 1???4?6?8... ck_?dc f ck_ahb ,max = 72 mhz ck_wdt wdten ck_hsi/16 ck_hse/16 ck_sys/16 ckout ckoutsrc[?:0] hseen hsien lseen (note1) lsien (note1 ) f ck_sys ,max = 144mhz ck_lsi ck_lse ck_?hb/16 ck_hsi ck_hse pclk (op?? ?fio? gpio port? ?dc? spi? us?rt? i ? c? gptm? mctm? bftm? exti? rtc? sci? watchdo? timer) pll clock monitor pllen ck_us?rt0 ck_us?rt1 f ck_usartn ,max = 72mhz ck_lse ck_pll urnen dm?en op?0en wdten ?dcen prescaler 1? ? f ck_pll ,max = 144mhz ck_lsi hclks ( to sr?m) hclkf ( to flash) cm?en fmcen cm?en sr?men 1 0 rtcsrc (note1 ) ck_rtc rtcen (note1) 1 0 1 0 note 1: those control bits are located at rtc control re?ister (rtc_ctrl) ck_?hb 000 001 010 011 100 101 110 ck_sys sw[1: 0] 0x 11 10 8 ck_usb f ck_usb ,max = 48mhz usben prescaler 1? ?? ? hclkc ( to cortex tm -m?) cm?en (control by hw) f csif_mck ,max = 24mhz csif_mck ck_csif ( to csif) csifen divider 2 csifmpre hclkbm ( to b?s matrix) cm?en bmen hclk?pb0 ( to ?pb0 brid?e) cm?en ?pb0en hclk?pb1 ( to ?pb1 brid?e) cm?en ?pb1en ck_mck ck_pll ( to csif clock o?tp?t) prescaler 1 ~ ?? csifmen ck_mck figure 3. HT32F1755/1765/2755 clock structure
rev. 1.00 ?1 of 45 ????st 1?? ?01? ??-bit ?rm cortex?-m? mcu ht??f1755/ht??f1765/ht??f?755 overview overview pin assignment 48 47 46 45 44 43 42 41 40 39 38 1 2 3 4 5 6 7 8 9 10 11 13 14 15 16 17 18 19 20 21 22 23 35 34 33 32 31 30 29 28 27 26 25 pa 0 adc _in 0 sci_dio pa 1 adc _in 1 ur0_tx gt1_ch1 pa 2 adc _in 2 ur0_rx gt1_ch2 pa 3 adc _in 3 ur1_rts / txe gt1_ch3 pa 4 adc _in 4 ur1_cts / sck pa 5 adc _in 5 ur1_tx spi1_mosi pa 6 adc _in 6 ur1_rx spi1_miso pa 7 adc _in 7 spi1_sck vdd 33_1 spi1_sel usbdp usbdm vss 33_3 vdd 33_3 ur0_cts mt_ch 1n i 2c0_sda pc 12 ur0_rts mt_ch 1 i 2c 0_scl pc 11 ur1_rx mt_ch 0n pe15 jtrst ur1_tx mt_ch 0 pe14 jtdi ur0_rx mt_eti sci_det pc 10 pc 9_ boot1 ur0_tx -- ckout pc 8_ boot0 xtalin af 0 ( default ) af 1 af2 af3 af 1 af 2 af 3 ( ht 32f1755) ( ht 32f1765) af 0 ( default) af 1 af 2 af 3 ( ht 32f1755) ( ht 32f1765) af 0 ( default ) af1 vldoin vssldo nrst vbat xtal32k in xtal32k out pb4 pb5 rtcout pb6_ wakeup pb11 pb12 vss 33_2 xtalout vdd 33_2 vssa pe8 vdda pe10 pe9 pe7 pe6 pe5 pd 11 pd 10 pd 8 cn 0 cp 0 aout0 cn 1 cp 1 aout1 gt 0_ch0 gt 0_ch2 gt 1_eti gt 0_eti gt 0_ch3 i 2c 1_sda i 2c1_scl spi1_sck spi1- sel p33 p33 bak 5 vt bak p33 bak 33 v bak 33 v bak 5 vt 5 vt 5 vt 5 vt p18 usb usb 33 v 33 v 33 v 33 v 33 v 33 v 33 v 33 v 33 v 33 v 33 v ap ap p33 ap p18 33 v 5 vt 5 vt 3.3 v digital power pad 3.3 v analog power pad 1.8 v power pad 3.3 v i/o pad 5 v tolerance i/o pad high current output 5 v tolerance i/o pad holtek HT32F1755/ 1765 / 2755 48 lqfp 37 12 24 36 vldoout pd 9 af 0 ( default ) 33 v sci_clk gt1_ch0 vss 33_1 p33 p33 33 v 33 v pe13 pe12 pe11 gt 0_ch1 spi0- sel spi0_sck spi0_mosi gt 1_ch0 gt 1_ch2 gt 1_ch3 gt 1_ch1 mt_ch 2 mt_ch 3 mt_brk mt_ch 2n p33 p33 5 vt 33 v 33 v csif _d0 csif _d1 csif _d2 csif _d3 csif _d4 csif _d5 csif _d6 csif _d7 af 3* ( ht 32f2755) af 3* ( ht 32f2755) p33 p33 5 vt 5 vt 5 vt 5 vt 5 vt 5 vt 5 vt 5 vt 5 vt 5 vt usb usb phy pad csif_mck csif_pck csif _vsync csif _hsync jtck _ swclk jtdo _ traceswo jtms_ swdio spi0_miso spi1_mosi spi1_miso bak backup domain pad figure 4. HT32F1755/1765/2755 48-lqfp pin assignment
rev. 1.00 ?? of 45 ????st 1?? ?01? ??-bit ?rm cortex?-m? mcu ht??f1755/ht??f1765/ht??f?755 overview 64 63 62 61 60 59 58 57 56 55 54 1 2 3 4 5 6 7 8 9 10 11 17 18 19 20 21 22 23 24 25 26 27 47 46 45 44 43 42 41 40 39 38 37 pa 0 adc _in 0 sci_dio pa 1 adc _in 1 ur0_tx gt1_ch1 pa 2 adc _in 2 ur0_rx gt1_ch2 pa 3 adc _in 3 ur1_rts gt1_ch3 pa 4 adc _in 4 ur1_cts pa 5 adc _in 5 ur1_tx spi1_mosi pa 6 adc _in 6 ur1_rx pa 7 adc _in 7 spi1_sck vdd 33_1 spi1_sel usbdp usbdm vss 33_3 vdd 33_3 ur0_cts mt_ch 1n i 2c0_sda pc 12 ur0_rts mt_ch 1 i 2c 0_scl pc 11 ur1_rx mt_ch 0n pe15 jtrst ur1_tx mt_ch 0 pe14 jtdi ur0_rx mt_eti sci_det pc 10 xtalin af 0 ( default ) af 1 af2 af3 af 1 af 2 af 3 ( ht 32f1755) ( ht 32f1765) af 0 ( default ) af 1 af 2 af 3 ( ht 32f1755) ( ht 32f1765) af 0 ( default) af 1 vldoin vssldo nrst vbat xtal32k in xtal32k out pb 4 pb 5 rtcout pb 6_ wakeup pb 11 pb 12 vss 33_2 xtalout vdd 33_2 vssa pe8 vdda pe10 pe9 pe7 pe6 pe5 pd 12 cn 0 cp 0 aout0 cn 1 cp 1 aout1 gt 0_ch0 gt 0_ch2 gt 1_eti gt 0_eti gt 0_ch3 i 2c1_sda i 2c 1_scl spi1_miso spi1_mosi spi1_sck spi1- sel p33 p33 bak 5 vt bak p33 bak 33 v bak 33 v bak 5 vt 5 vt 5 vt 5 vt p18 usb usb 33 v 33 v 33 v 33 v 33 v 33 v 33 v 33 v 33 v 33 v 33 v ap ap p33 ap p18 33 v 5 vt 5 vt 3.3 v digital power pad 3 .3 v analog power pad 1.8 v power pad 3.3 v i/o pad 5 v tolerance i/o pad high current output 5 v tolerance i/o pad holtek HT32F1755/ 1765 / 2755 64 lqfp 53 12 28 48 vldoout pd 13 af 0 ( default ) 33 v sci_clk gt1_ch0 vss 33_1 p33 p33 33 v pe13 pe12 pe11 gt 0_ch1 mt_ch 0 mt_ch 0n gt 1_eti gt 0_eti i 2c 0_scl i 2c0_sda p33 p33 5 vt 5 vt 33 v 33 v csif_d4 csif_d5 csif_d6 csif_d7 csif_mck csif_pck csif _vsync csif _hsync af 3* ( ht 32f2755) af 3* ( ht 32f2755) 5 vt 5 vt p33 p33 13 14 15 pb 0 pb 2 pb 3 16 pb 1 29 30 31 pc 0 pb 7 pc 1 pc 2 32 33 v 52 51 50 pd 11 pd 10 pd 8 49 pd 9 spi0- sel spi0_sck spi0_mosi spi0_miso gt 1_ch0 gt 1_ch2 gt 1_ch3 gt 1_ch1 mt_ch 2 mt_ch 3 mt_brk mt_ch 2n csif_d0 csif_d1 csif_d2 csif_d3 36 35 34 33 ur0_tx ckout pc 9_ boot1 pc 8_ boot0 ur0_dcd gt 1_ch3 spi1_miso pc 3 5 vt 5 vt 5 vt 5 vt 5 vt 5 vt ur1_rts gt0_ch0 ur1_cts gt0_ch1 ur1_tx spi0_mosi gt0_ch2 ur1_rx spi0_miso gt0_ch3 spi0_sck spi0_sel 5 vt gt 0_eti i2c1_sda ur0_dtr spi1_sel gt1_ch0 spi1_sck gt1_ch1 spi1_mosi gt1_ch2 i2c1_scl i2c1_sda ur0_ri -- ur1_cts mt_ch 0n sci _ dio pc 14 ur1_rts mt_ch 0 sci _clk pc 13 ur 0_dsr gt 0_eti sci_det pc 15 p33 p33 vdd 33_4 vss 33_4 af2 af3 5 vt 5 vt 5 vt 5 vt 5 vt 5 vt 5 vt 5 vt 5 vt 5 vt 5 vt 5 vt 5 vt usb usb phy pad 5 vt spi1_miso jtck _ swclk jtdo _ traceswo jtms_ swdio bak backup domain pad figure 5. HT32F1755/1765/2755 64-lqfp pin assignment
rev. 1.00 ?? of 45 ????st 1?? ?01? ??-bit ?rm cortex?-m? mcu ht??f1755/ht??f1765/ht??f?755 overview overview 100 99 98 97 96 95 94 93 92 91 81 1 2 3 4 5 6 7 8 14 15 16 26 27 28 29 30 31 32 33 34 35 36 66 65 64 63 62 61 60 59 58 57 56 pa 0 adc _in 0 sci_dio pa 1 adc _in 1 ur0_tx gt1_ch1 pa 2 adc _in 2 ur0_rx gt1_ch2 pa 3 adc _in 3 ur1_rts gt1_ch3 pa 4 adc _in 4 ur1_cts pa 5 adc _in 5 ur1_tx spi1_mosi pa 6 adc _in 6 ur1_rx pa 7 adc _in 7 spi1_sck vdd 33_1 spi1_sel usbdp usbdm vss 33_3 vdd 33_3 ur0_cts mt_ch 1n i 2c0_sda pc 12 ur0_rts mt_ch 1 i 2c 0_scl pc 11 ur1_rx mt_ch 0n pe15 jtrst ur1_tx mt_ch 0 pe14 jtdi jtck _ swclk jtdo _ traceswo ur0_rx mt_eti sci_det pc 10 xtalin af 0 ( default ) af 1 af2 af3 af 1 af 2 af 3 ( ht 32f1755) ( ht 32f1765) af 0 ( default ) af 1 af 2 af 3 ( ht 32f1755) ( ht 32f1765) af 0 ( default) af 1 vldoin vssldo nrst vbat xtal32kin xtal32kout pb 4 pb 5 rtcout pb 6_ wakeup pb 11 pb 12 vss 33_2 xtalout vdd 33_2 vssa pe8 vdda pe10 pe9 pe7 pe6 pe5 pd 12 cn 0 cp 0 aout0 cn 1 cp 1 aout1 gt 0_ch0 gt 0_ch2 gt 1_eti gt 0_eti gt 0_ch3 i 2c1_sda i 2c 1_scl spi1_miso spi1_mosi spi1_sck spi1- sel p33 p33 bak 5 vt bak p33 bak 33 v bak 33 v bak 5 vt 5 vt 5 vt 5 vt p18 usb usb 33 v 33 v 33 v 33 v 33 v 33 v 33 v 33 v 33 v 33 v 33 v ap ap p33 ap p18 33 v 5 vt 5 vt 3.3 v digital power pad 3.3 v analog power pad 1.8 v power pad 3.3 v i/o pad 5 v tolerance i/o pad high current output 5 v tolerance i/o pad holtek HT32F1755/ 1765 / 2755 100 lqfp 80 17 37 67 vldoout jtms_ swdio pd 13 af 0 ( default ) 33 v sci_clk gt1_ch0 vss 33_1 p33 p33 33 v pe13 pe12 pe11 gt 0_ch1 mt_ch 0 mt_ch 0n gt 1_eti gt 0_eti i 2c 0_scl i 2c0_sda p33 p33 5 vt 5 vt csif_d4 csif_d5 csif_d6 csif_d7 af 3* ( ht 32f2755) af 3* ( ht 32f2755) 5 vt 5 vt p33 p33 9 10 11 pa 8 pa 10 pa 11 12 pa 9 38 39 40 pb 13 pb 7 pb 14 pb 15 41 33 v 79 78 77 pd 11 pd 10 pd 8 76 pd 9 spi0- sel spi0_sck spi0_mosi spi0_miso gt 1_ch0 gt 1_ch2 gt 1_ch3 gt 1_ch1 mt_ch 2 mt_ch 3 mt_brk mt_ch 2n csif_d0 csif_d1 csif_d2 csif_d3 55 54 53 52 ur0_tx ckout pc 9_ boot1 pc 8_ boot0 sci _ dio i 2c1_sda pc 7 5 vt 5 vt 5 vt 5 vt 5 vt 5 vt ur0_rts ur0_cts ur0_tx ur0_rx 5 vt gt 0_eti i2c1_sda ur0_dtr ur0_rx ur1_cts gt1_eti ur1_rts -- ur1_cts mt_ch 0n sci _ dio pc 14 ur1_rts mt_ch 0 sci _clk pc 13 ur 0_dsr gt 0_eti sci_det pc 15 af2 af3 5 vt 5 vt 5 vt 5 vt 5 vt 5 vt 5 vt 5 vt 5 vt usb usb phy pad pa 12 13 5 vt gt1_ch0 18 19 20 pa 13 pa 15 pb 0 21 pa 14 5 vt 5 vt 5 vt 5 vt gt1_ch1 gt1_ch2 gt1_ch3 gt0_ch0 pb 1 22 5 vt gt0_ch1 23 pb 2 pb 3 24 5 vt 5 vt gt0_ch2 gt0_ch3 nc 25 5 vt 42 43 pc 0 pc 1 pc 2 44 spi1_sel gt1_ch0 spi1_sck gt1_ch1 spi1_mosi gt1_ch2 i2c1_scl i2c1_sda ur0_ri 45 46 pc 3 pc 4 pc 5 47 spi1_miso gt1_ch3 ur1_tx ur1_rx ur0_dcd 5 vt 5 vt 5 vt 48 49 50 5 vt 83 pd 14 82 pd 15 mt_ch 1 mt_ch 1n sci _clk sci _ dio 5 vt 5 vt 85 pe0 84 mt_ch 2 5 vt 87 86 pe1 mt_ch 2n 5 vt 89 pe2 88 pe3 mt_ch 3 mt_brk 5 vt 5 vt 90 pe4 mt_eti 5 vt 51 sci _clk i 2c 1_scl pc 6 68 ur 0_dtr pd 0 69 ur 0_ri pd 1 70 ur0_dcd pd 2 72 71 spi1_sel pd 4 pd 3 5 vt 5 vt 74 73 spi1_mosi pd 6 spi1_sck pd 5 5 vt 5 vt 75 spi1_miso pd 7 5 vt spi1_miso spi1_mosi spi1_sck spi1_sel spi1_miso ur1_rts ur1_cts ur1_tx ur1_rx spi0_mosi spi0_sck spi0_sel spi0_miso pb 8 ur0_rts pb 9 ur0_cts pb 10 ur0_tx 5 vt 5 vt 5 vt i2c0_scl i2c0_sda spi0_sel spi0_mosi spi0_sck spi0_miso gt 0_ch3 gt 0_ch2 gt 0_ch1 gt 0_ch0 p33 p33 vdd 33_4 vss 33_4 33 v 33 v ap ap vref- vref+ csif_mck csif_pck csif _vsync csif _hsync 5 vt 5 vt 5 vt 5 vt 5 vt 5 vt 5 vt 5 vt 5 vt 5 vt 5 vt bak backup domain pad figure 6. HT32F1755/1765/2755 100-lqfp pin assignment
rev. 1.00 ?4 of 45 ????st 1?? ?01? ??-bit ?rm cortex?-m? mcu ht??f1755/ht??f1765/ht??f?755 overview table 2. HT32F1755/1765/2755 pin descriptions pin name pins type (note1) io level (note2) description 48 lqfp 64 lqfp 100 lqfp main function (af0) af1 af2 af3 (HT32F1755) (ht32f1765) af3 (ht32f2755) p? 0 1 1 1 ?i/o p? 0 ?dc_ in0 sci_clk gt1_ch0 gt1_ch0 p? 1 ? ? ? ?i/o p? 1 ?dc_ in1 sci_dio gt1_ch1 gt1_ch1 p ?? ? ? ? ? i/o p ?? ?dc_ in? ur0_tx gt1_ch? gt1_ch? p ?? 4 4 4 ? i/o p ?? ?dc_ in? ur0_rx gt1_ch? gt1_ch? p? 4 5 5 5 ? i/o p? 4 ?dc_ in4 ur1_rts /txe spi1_sel spi1_sel p? 5 6 6 6 ? i/o p? 5 ?dc_ in5 ur1_cts /sck spi1_sck spi1_sck p? 6 7 7 7 ? i/o p? 6 ?dc_ in6 ur1_tx spi1_mosi spi1_mosi p? 7 8 8 8 ? i/o p? 7 ?dc_ in7 ur1_rx spi1_miso spi1_miso p? 8 9 i/o 5v-t p? 8 spi1_sel ur0_rts /txe p? 9 10 i/o 5v-t p? 9 spi1_sck ur0_cts /sck p ?10 11 i/o 5v-t p ?10 spi1_mosi ur0_tx p? 11 1? i /o 5v-t p? 11 spi1_miso ur0_rx p ?1? 1? i/o 5v-t p ?1? gt1_ch0 vdd??_1 9 9 14 p ?.?v volta?e for di?ital i/o vss??_1 10 10 15 p gro?nd reference for di?ital i/o usbdp 11 11 16 ?i/o usb differential data b ?s conformin? to the universal serial b?s standard usbdm 1? 1? 17 ?i/o usb differential data b ?s conformin? to the universal serial b?s standard p ?1? 18 i/o 5v-t p ?1? gt1_ch1 p ?14 19 i/o 5v-t p ?14 gt1_ch? p ?15 ?0 i/o 5v-t p ?15 gt1_ch? pb0 1? ?1 i/o 5v-t pb0 gt0_ch0 ur1_rts /txe spi0_sel spi0_sel pb1 14 ?? i/o 5v-t pb1 gt0_ch1 ur1_cts /sck spi0_sck spi0_sck pb? 15 ?? i/o 5v-t pb? gt0_ch? ur1_tx spi0_mosi spi0_mosi pb? 16 ?4 i/o 5v-t pb? gt0_ch? ur1_rx spi0_miso spi0_miso nc ?5 no connection vldoout 1? 17 ?6 p ldo 1.8v o?tp?t it is recommended to connect a capacitor ? denoted as c ldo ? as close as possible between this pin and vssldo vldoin 14 18 ?7 p ldo ?.?v power inp?t c onnected to the power switch circ?itry for the internal back?p domain vssldo 15 19 ?8 p ldo ?ro?nd reference nrst 16 ?0 ?9 i (bk) 5v- t_pu external reset pin and external wake?p pin in power-down mode vb? t 17 ?1 ?0 p vdd ?.?v for back?p domain
rev. 1.00 ?5 of 45 ????st 1?? ?01? ??-bit ?rm cortex?-m? mcu ht??f1755/ht??f1765/ht??f?755 overview overview pin name pins type (note1) io level (note2) description 48 lqfp 64 lqfp 100 lqfp main function (af0) af1 af2 af3 (HT32F1755) (ht32f1765) af3 (ht32f2755) xt ?l- ??kin 18 ?? ?1 ? i/o (bk) xt ?l??kin pb4 xt ?l- ??kout 19 ?? ?? ? i/o (bk) xt ?l??kout pb5 rtcout ?0 ?4 ?? i/o (bk) 5v-t rtcout pb6_ w ?keup pb7 ?5 ?4 i/o 5v-t pb7 gt0_eti i?c1_ sd? ur0_dtr ur0_dtr pb8 ?5 i/o 5v-t pb8 ur0_rts /txe pb9 ?6 i/o 5v-t pb9 ur0_cts /sck pb10 ?7 i/o 5v-t pb10 ur0_tx xt ?lin ?1 ?6 ?8 ?i/o xt ?lin pb11 xt ?lout ?? ?7 ?9 ?i/o xt ?lout pb1? vdd??_? ?? ?8 40 p ?.?v volta?e for di?ital i/o vss??_? ?4 ?9 41 p gro?nd reference for di?ital i/o pb1? 4? i/o 5v-t pb1? ur0_rx pb14 4? i/o 5v-t pb14 ur1_cts /sck gt1_eti pb15 44 i/o 5v-t pb15 ur1_rts /txe pc0 ?0 45 i/o 5v-t pc0 spi1_sel gt1_ ch0 i?c1_scl i?c1_scl pc1 ?1 46 i/o 5v-t pc1 spi1_sck gt1_ ch1 i?c1_sd? i?c1_sd? pc? ?? 47 i/o 5v-t pc? spi1_ mosi gt1_ ch? ur0_ri ur0_ri pc? ?? 48 i/o 5v-t pc? spi1_ miso gt1_ ch? ur0_dcd ur0_dcd pc4 49 i/o 5v-t pc4 ur1_tx i?c0_ scl pc5 50 i/o 5v-t pc5 ur1_rx i?c0_ sd? pc6 51 i/o 5v-t pc6 i?c1_scl sci_ clk pc7 5? i/o 5v-t pc7 i?c1_sd? sci_dio pc8 ?5 ?4 5? i/o 5v-t_ pu pc8_boot0 ckout ur0_tx ur0_tx pc9 ?6 ?5 54 i/o 5v-t_ pu pc9_boot1 pc10 ?7 ?6 55 i/o 5v-t pc10 sci _det mt_eti ur0_rx ur0_rx pe11 ?8 ?7 56 i/o 5v-t jtdo_ tr?ceswo pe11
rev. 1.00 ?6 of 45 ????st 1?? ?01? ??-bit ?rm cortex?-m? mcu ht??f1755/ht??f1765/ht??f?755 overview pin name pins type (note1) io level (note2) description 48 lqfp 64 lqfp 100 lqfp main function (af0) af1 af2 af3 (HT32F1755) (ht32f1765) af3 (ht32f2755) pe1? ?9 ?8 57 i/o 5v- t_pu jtck_ swclk pe1? pe1? ?0 ?9 58 i/o 5v- t_pu jtms/ swdio pe1? pe14 ?1 40 59 i/o 5v- t_pu jtdi pe14 mt_ch0 ur1_tx csif_ hsync pe15 ?? 41 60 i/o 5v- t_pu jtrst pe15 mt_ ch0n ur1_rx csif_ vsync vdd??_? 4? 61 p ?.?v volta?e for di?ital i/o vss??_ ? 4? 6? p gro?nd reference for di?ital i/o pc11 ?? 44 6? i/o 5v-t pc11 i?c0_scl mt_ch1 ur0_rts /txe csif_pck p c1? ?4 45 64 i/o 5v-t p c1? i?c0_sd? mt_ ch1n ur0_cts /sck csif_mck p c1? 46 65 i/o 5v-t p c1? sci_clk mt_ch0 ur1_rts /txe ur1_rts /txe pc14 47 66 i/o 5v-t pc14 sci_dio mt_ ch0n ur1_cts /sck ur1_cts /sck pc15 48 67 i/o 5v-t pc15 sci_det gt0_eti ur0_dsr ur0_dsr pd0 68 i/o 5v-t pd0 gt0_ch0 spi0_ sel ur0_dtr ur0_dtr pd1 69 i/o 5v-t pd1 gt0_ch1 spi0_ sck ur0_ri ur0_ri pd? 70 i/o 5v-t pd? gt0_ch? spi0_ mosi ur0_dcd ur0_dcd pd? 71 i/o 5v-t pd? gt0_ch? spi0_ miso pd4 7? i/o 5v-t pd4 spi1_sel pd5 7? i/o 5v-t pd5 spi1_sck pd6 74 i/o 5v-t pd6 spi1_ mosi pd7 75 i/o 5v-t pd7 spi1_ miso vdd??_? ?5 p ?.?v volta?e for di?ital i/o vss??_? ?6 p gro?nd reference for di?ital i/o pd8 ?7 49 76 i/o 5v-t pd8 spi0_sel mt_ch? gt1_ch0 csif_d0 pd9 ?8 50 77 i/o 5v-t pd9 spi0_sck mt_ ch?n gt1_ch1 csif_d1 pd10 ?9 51 78 i/o 5v-t pd10 spi0_ mosi mt_ch? gt1_ch? csif_d? pd11 40 5? 79 i/o 5v-t pd11 spi0_ miso mt_brk gt1_ch? csif_d? pd1? 5? 80 i/o 5v-t pd1? mt_ch0 i?c0_ scl gt1_eti gt1_eti
rev. 1.00 ?7 of 45 ????st 1?? ?01? ??-bit ?rm cortex?-m? mcu ht??f1755/ht??f1765/ht??f?755 overview overview pin name pins type (note1) io level (note2) description 48 lqfp 64 lqfp 100 lqfp main function (af0) af1 af2 af3 (HT32F1755) (ht32f1765) af3 (ht32f2755) pd1? 54 81 i/o 5v-t pd1? mt_ch0n i?c0_ sd? gt0_eti gt0_eti pd14 8? i/o 5v-t pd14 mt_ch1 sci_ clk pd15 8? i/o 5v-t pd15 mt_ch1n sci_dio pe0 84 i/o 5v-t pe0 mt_ch? v dd??_4 55 85 p ?.?v volta?e for di?ital i/o v ss??_4 56 86 p gro?nd reference for di?ital i/o pe1 87 i/o 5v-t pe1 mt_ch?n pe? 88 i/o 5v-t pe? mt_ch? pe? 89 i/o 5v-t pe? mt_brk pe4 90 i/o 5v-t pe4 mt_eti pe5 41 57 91 ? i/o pe5 cn0 gt0_ ch0 spi1_sel csif_d4 pe6 4? 58 9? ? i/o pe6 cp0 gt0_ ch1 spi1_sck csif_d5 pe7 4? 59 9? ? i/o pe7 ?out0 gt0_ ch? spi1_ mosi csif_d6 pe8 44 60 94 ? i/o pe8 cn1 gt0_ ch? spi1_ miso csif_d7 pe9 45 61 95 ? i/o pe9 cp1 gt0_eti i?c1_scl i?c1_scl pe10 46 6? 96 ? i/o pe10 ?out1 gt1_eti i?c1_sd? i?c1_sd? vdd? 47 6? 97 p ?.? v a nalo? volta?e for ?dc and op ?/comparator vref+ 98 p ?dc positive reference volta?e has to be lower or eq?al to vdd? vref- 99 p ?dc ne?ative reference volta?e has to be directly connect ed to vss? vss? 48 64 100 p gro?nd reference for the ?dc and op ?/comparator notes: 1. i = inp?t? o = o?tp?t? ? = ?nalo? port? p = power s?pply ? pu = p?ll-?p? bk = back-?p domain. 2. 5v-t = 5v tolerant. 3. the gpios are in an ?f0 state after a v dd18 power on reset (por) except for the rtcout pin of in the back? p domain i/o. the rtcout pin is reset by the back? p domain power-on-reset (porb) or by a back?p domain software reset (b? k_rst bit in b?k_cr re?ister). 4. the back ?p domain of i/o pins has drive c?rrent capability limitation of < 1m? @ v b ?t = ?.? v.
rev. 1.00 ?8 of 45 ????st 1?? ?01? ??-bit ?rm cortex?-m? mcu ht??f1755/ht??f1765/ht??f?755 electrical characteristics 4 electrical characteristics absolute maximum ratings the following table shows the absolute maximum ratings of the device. these are stress ratings only. stresses beyond absolute maximum ratings may cause permanent damage to the device. note that the device is not guaranteed to operate properly at the maximum ratings. exposure to the absolute maximum rating conditions for extended periods may affect device reliability. table 3. absolute maximum ratings symbol parameter min max unit v dd?? external main s?pply volta?e v ss - 0.? v ss + ?.6 v v dd? external analo? s?pply volta?e v ss? - 0.? v ss? + ?.6 v v b ?t external battery s?pply volta?e v ss - 0.? v ss + ?.6 v v ldoin external ldo s?pply volta?e v ss - 0.? v ss + ?.6 v v in inp?t volta? e on 5v-tolerant i/o v ss - 0.? v ss + 5.5 v inp?t volta?e on other i/o v ss - 0.? v dd?? + 0.? v t ? ?mbient operatin? temperat?re ran?e -40 +85 c t stg stora?e temperat?re ran?e -55 +150 c t j maxim?m j?nction temperat?re 1?5 c p d total power dissipation 500 mw v esd electrostatic dischar?e volta?e (h?man body mode) -4000 +4000 v recommended dc characteristics table 4. recommended dc operating conditions t ? = 25c, unless otherwise specifed. symbol parameter conditions min typ max unit v dd?? i/o operatin? volta?e ?.7 ?.? ?.6 v v dd? ?nalo? operatin? volta?e ?.7 ?.? ?.6 v v b ?t battery s?pply operatin? volta?e ?.7 ?.? ?.6 v v ldoin ldo operatin? volta?e ?.7 ?.? ?.6 v on-chip ldo voltage regulator characteristics table 5. ldo characteristics t ? = ?5 c, unless otherwise specifed. symbol parameter conditions min typ max unit v ldoout internal re??lator o?tp?t volta?e v ldoin = ?.?v re??lator inp?t 1.71 1.8 1.89 v i ldoout o?tp?t c?rrent v ldoin = ?.7v re??lator inp?t ?00 m? c ldo external flter capacitor value for internal core power s?pply the capacitor val?e is dependent on the core power c?rrent cons?mption ?.? 10 f
rev. 1.00 ?9 of 45 ????st 1?? ?01? ??-bit ?rm cortex?-m? mcu ht??f1755/ht??f1765/ht??f?755 electrical characteristics electrical characteristics power consumption table 6. power consumption characteristics t ? = ?5 c, unless otherwise specifed. symbol parameter conditions min typ max unit i dd s?pply c?rrent (r?n mode) v dd?? = v b ?t = ?.?v ? hse = 8mhz? pll = 144mhz? f hclk = 7?mhz? f pclk = 7?mhz? ?ll peripherals enabled 60 7? m? v dd?? = v b ?t = ?.?v ? hse = 8mhz? pll = 144mhz? f hclk = 7?mhz? f pclk = 7?mhz? ?ll peripherals disabled ?7 ?4 m? s?pply c?rrent (sleep mode) v dd = v b ?t = ?.?v ? hse = 8mhz? pll = 144mhz? f hclk = 0mhz? f pclk = 7?mhz? ?ll peripherals enabled 4? 50 m? v dd?? = v b ?t = ?.?v ? hse = 8mhz? pll = 144mhz? f hclk = 0mhz? f pclk = 7?mhz? ?ll peripherals disabled 9 1? m? s?pply c?rrent (deep-sleep1 mode) v dd?? = v b ?t = ?.?v ? ? ll clock off (hse/pll/f hclk )? ldo in low power mode , lsi on? rtc on 58 90 a s?pply c?rrent (deep-sleep? mode) v dd?? = v b ?t = ?.?v ? ? ll clock off (hse/pll/f hclk )? ldo off (dmos on) , lsi on? rtc on 18 ?5 a s?pply c?rrent (power-down mode) v dd?? = v b ?t = ?.?v ? ldo off? lse on? lsi off? rtc on a v dd?? = v b ?t = ?.?v ? ldo off? lse on? lsi off? rtc off a v dd?? = v b ?t = ?.?v ? ldo off? lse off? lsi on? rtc on a v dd?? = v b ?t = ?.?v ? ldo off? lse off? lsi on? rtc off 5 6 a i b ?t battery s?pply c?rrent (power- down mode) v dd?? not present? v b ?t = ?.?v ? ldo off? lse off? lsi on? rtc on 4 a v dd?? not present? v b ?t = ?.?v ? ldo off? lse off? lsi on? rtc off ?.9 a notes: 1. hse is the hi? h speed external oscillator. hsi means 8mhz hi? h speed internal oscillator. 2. lse means low speed external oscillator. lsi means ?? .768khz low speed internal oscillator. 3. rtc means real time clock. 4. code = while (1) { ? 08 nop } exec?ted in flash. reset and supply monitor characteristics table 7. lvd/bod characteristics t ? = ?5 c, unless otherwise specifed. symbol parameter conditions min typ max unit v bod brown o? t detector volta?e ?.6 v v lvd volta ? e of low volta?e detector lvds (note1) = 00 ?.7 v lvds (note1) = 01 ?.8 v lvds (note1) = 10 ?.9 v lvds (note1) = 11 ?.0 v v por power on reset volta ?e 1.?6 v note: lvds feld is in pwrcu lvdcsr register.
rev. 1.00 ?0 of 45 ????st 1?? ?01? ??-bit ?rm cortex?-m? mcu ht??f1755/ht??f1765/ht??f?755 electrical characteristics external clock characteristics table 8. high speed external clock (hse) characteristics t ? = ?5 c, unless otherwise specifed. symbol parameter conditions min typ max unit f hse hi?h speed external oscillator freq?ency (hse) v dd?? = ?.?v 4 16 mhz c hse recommended load capacitance on xt ?l??in and xt ?l?? out pins tbd pf r fhse recommended external feedback resistor between xt ?l??in and xt ?l?? out pins 1.0 m d hse hse oscillator d?ty cycle 40 60 % i ddhse hse oscillator operatin? c?rrent v dd?? = ?.?v ? t ? = ?5c 0.96 m? i stbhse hse oscillator standby c?rrent v dd?? = ?.?v ? t ? = ?5c 0.1 a t suhse hse oscillator start?p time v dd?? = ?.?v ? t ? = ?5c 4 ms table 9. low speed external clock (lse) characteristics t ? = ?5 c, unless otherwise specifed. symbol parameter conditions min typ max unit f lse low speed external oscillator freq?ency (lse) v dd?? = v b ?t = ?.?v ??.768 khz c lse recommended load capacitance on xt ?l??kin and xt ?l?? kout pins tbd pf r flse recommended external feedback resistor between xt ?l??kin and xt ?l?? kout pins 10 m d lse lse oscillator d?ty cycle 40 60 % i ddlse lse oscillator operatin? c?rrent v dd?? = v b ?t = ?.?v ? lsesm = 0 (normal start?p mode) 1.7 a i stblse lse oscillator standby c?rrent v dd?? = v b ?t = ?.?v ? lsesm = 1 (fast start?p mode) ? 8 a t sulse lse oscillator start?p time v dd?? = v b ? t = ?.?v ? lsesm = 1 (fast start?p mode) ?00 ms
rev. 1.00 ?1 of 45 ????st 1?? ?01? ??-bit ?rm cortex?-m? mcu ht??f1755/ht??f1765/ht??f?755 electrical characteristics electrical characteristics internal clock characteristics table 10. high speed internal clock (hsi) characteristics t ? = ?5 c, unless otherwise specifed. symbol parameter conditions min typ max unit f hsi hi?h speed internal oscillator freq?ency (hsi ) v dd?? = ?.?v ? t ? = -40c ~ +85c 8 mhz ?cc hsi hsi oscillator freq?ency acc?racy factory-trimmed? v dd?? = ?.?v ? t ? = -40c ~ +85c -5 +5 % d hsi hsi oscillator d?ty cycle v dd?? = ?.?v ? f hsi = 8mhz ?5 65 % i ddhsi hsi oscillator operatin? c?rrent v dd?? = ?.?v ? f hsi = 8mhz 0.9? m? t suhsi hsi oscillator start?p time v dd?? = ?.?v ? f hsi = 8mhz? hsircbl = 0 (hsi ready co?nter bits len?th 7 bits ) 17 s note: hsircbl feld is in pwrcu hsircr register. table 11. low speed internal clock (lsi) characteristics t ? = ?5 c, unless otherwise specifed. symbol parameter conditions min typ max unit f lsi low speed internal oscillator freq?ency(lsi) v dd?? = v b ?t = ?.?v ? t ? = -40 c ~ +85c ?5 ?? 4? khz i ddlsi lsi oscillator operatin? c?rrent v dd?? = v b ?t = ?.?v ? t ? = ?5 c 1.0 ? a t sulsi lsi oscillator start?p time v dd?? = v b ?t = ?.?v ? t ? = ?5 c ?5 ms pll characteristics table 12. pll characteristics t ? = ?5 c, unless otherwise specifed. symbol parameter conditions min typ max unit f pllin pll inp ?t clock 4 16 mhz f pll pll o ?tp?t clock 8 144 mhz t lock pll lock time tbd ms memory characteristics table 13. flash memory characteristics t ? = ?5 c, unless otherwise specifed. symbol parameter conditions min typ max unit n endu n?mber of ??aranteed pro?ram /erase cycles before fail?re. (end?rance) t ? = -40c ~ +85c ?0 kcycles t ret data retention time t ? = ?5c 100 years t prog word pro ?rammin? time t ? = -40c ~ +85c 40 s t er?se pa?e erase time t ? = -40c ~ +85c ?0 40 ms t mer?se mass erase time t ? = -40c ~ +85c ?0 40 ms
rev. 1.00 ?? of 45 ????st 1?? ?01? ??-bit ?rm cortex?-m? mcu ht??f1755/ht??f1765/ht??f?755 electrical characteristics i/o port characteristics table 14. i/o port characteristics t ? = ?5 c, unless otherwise specifed. symbol parameter conditions min typ max unit i il low level inp?t c?rrent ?.?v io v i = 0v ? on-chip p?ll-?p resister disabled. ? a 5v-tolerant io ? a reset pin ? a i ih hi?h level inp?t c?rrent ?.?v io v i = v dd??? on-chip p?ll- down resister disabled. ? a 5v-tolerant io ? a reset pin ? a v il low level inp?t volta?e ?.?v io -0.? 0.8 v 5v-tolerant io -0.? 0.8 v reset pin -0.? 0.8 v v ih hi?h level inp?t volta?e ?.?v io ? ?.6 v 5v-tolerant io ? 5.5 v reset pin ? 5.5 v v hys schmitt tri ?? er inp?t volta ?e hysteresis ?.?v io 400 mv 5v-tolerant io 400 mv reset pin 400 mv i ol low level o?tp?t c?rrent (gpo sink c?rrent) ?.?v io 4m? drive? v ol = 0.4v 4 m? ?.?v io 8m? drive? v ol = 0.4v 8 m? 5v-tolerant 8m ? drive io? v ol =0.4v 8 m? 5v-tolerant 1 ?m? drive io? v ol =0.4v 1? m? back?p domain io drive @ v b ?t =?.?v ? v ol = 0.4v ? pb4? pb5? pb6 1 m? i oh hi?h level o?tp?t c?rrent (gpo so?rce c?rrent) ?.?v i/o 4m? drive? v oh =v dd?? - 0.4v 4 m? ?.?v i/o 8m? drive? v oh =v dd?? - 0.4v 8 m? 5v-tolerant i/o 8m ? drive? v oh = v dd?? - 0.4v 8 m? 5v-tolerant i/o 1 ?m? drive? v oh = v dd?? - 0.4v 1? m? back?p domain io drive@v b ?t =?.?v ? v oh = v dd?? - 0.4v ? pb4? pb5? pb6 1 m? v ol low level o?tp?t volta?e ?.?v 4m? drive io? i ol = 4m? 0.4 v ?.?v 8m? drive io? i ol = 8m? 0.4 v 5v-tolerant 8m ? drive io? i ol =8m? 0.4 v 5v-tolerant 1 ?m? drive io? i ol =1?m? 0.4 v v oh hi?h level o?tp?t volta?e ?.?v 4m? drive io? i oh = 4m? v dd?? - 0.4v v ?.?v 8m? drive io? i oh = 8m? v dd?? - 0.4v v 5v-tolerant 8m ? drive io? i oh =8m? v dd?? - 0.4v v 5v-tolerant 1 ?m? drive io? i oh =1?m? v dd?? - 0.4v v
rev. 1.00 ?? of 45 ????st 1?? ?01? ??-bit ?rm cortex?-m? mcu ht??f1755/ht??f1765/ht??f?755 electrical characteristics electrical characteristics symbol parameter conditions min typ max unit r pu internal p?ll-?p resistor ?.?v i/o ?4 74 k 5v-tolerant i/o ?8 89 k r pd internal p? ll-down resistor ?.?v i/o ?9 86 k 5v-tolerant i/o ?5 107 k adc characteristics table 15. adc characteristics t ? = ?5 c, unless otherwise specifed. symbol parameter conditions min typ max unit v dd? operatin? volta?e ?.7 ?.? ?.6 v v ?dcin ?/d converter inp?t volta?e ran?e 0 v ref+ v v ref+ ?/d converter reference volta?e v dd? v dd? v i ?dc c?rrent cons?mption v dd? = ?.?v 1 tbd m? i ?dc_dn power down c?rrent cons?mption v dd? = ?.?v 1 10 a f ?dc ?/d converter clock 0.7 14 mhz f s samplin? rate 0.05 1 mhz f ?dcconv ?/d converter conversion time 14 1/f ?dc cycles r i inp?t samplin? switch resistance 1 k c i inp?t samplin? capacitance no pin/pad capacitance incl?ded 5 pf t su start ?p time 1 s n resol?tion 1? bits inl inte?ral non-linearity error f s = 1mhz? v dd? = ?.?v - ? 5 lsb dnl differential non-linearity error f s = 1mhz? v dd? = ?.?v 1 lsb e o offset error 10 lsb e g gain error 10 lsb notes: 1. g?aranteed by desi?n? not tested in prod?ction. 2. the fi ??re below shows the eq?ivalent circ?it of the ?/d converter sample-and-hold inp?t sta? e where c i is the stora?e capacitor ? ri is the resistance of the samplin? switch and r s is the o?tp? t impedance of the si ?nal so?rce v s . normally the samplin ? phase d?ration is approximately ? 1.5/f ?dc . the capacitance? c i ? m?st be char?ed within this time frame and it m?st be ens?red that the volta?e at its terminals becomes suffciently close to v s for acc? racy. to ?? arantee this? r s may not have an arbitrarily lar?e val?e.
rev. 1.00 ?4 of 45 ????st 1?? ?01? ??-bit ?rm cortex?-m? mcu ht??f1755/ht??f1765/ht??f?755 electrical characteristics sar adc c i sample r i r s v s figure 7. adc sampling network model the worst case occurs when the extremities of the input range (0v and v ref ) are sampled consecutively. in this situation a sampling error below 1/4 lsb is ensured by using the following equation: i n i adc s r c f r ? < + ) 2 ln( 5 . 1 2 where f adc is the adc clock frequency and n is the adc resolution (n = 12 in this case). a safe margin should be considered due to the pin/pad parasitic capacitances, which are not accounted for in this simple model. if, in a system where this a/d converter is used, there are no rail-to-rail input voltage variations between consecutive sampling phases, rs may be larger than the value indicated by the equation above.
rev. 1.00 ?5 of 45 ????st 1?? ?01? ??-bit ?rm cortex?-m? mcu ht??f1755/ht??f1765/ht??f?755 electrical characteristics electrical characteristics operation amplifer/comparator characteristics table 16. opa/cmp characteristics t ? = ?5 c , unless otherwise specifed. symbol parameter conditions min typ max unit v dd? operatin? volta?e ?.7 ?.? ?.6 v i op ?/cmp typical operatin ? c?rrent ??0 a i op ?/cmp_dn power down s?pply c?rrent ?ssi?n re?isters op ?en = 0 and en_op ? op = 0 0.1 a v ios inp? t offset volta?e v dd? = ?.?v ? ?nof[5:0] = 100000 -15 15 mv v dd? = ?.?v ? ?fter calibration -1 1 mv v ios_drift inp? t offset volta?e drift t ? = -40c ~ +85c 0.04 mv/c r input inp?t resistance 10 m? gv volta ?e gain 60 100 db u t unit-gain bandwidth r l = 100k 1.? mhz r l = 100k, c l = 100pf 1.?4 v cm common mode volta?e ran?e v dd? = ?.?v v ss? v dd? C 1.? v v ov op ? o?tp?t volta?e swin? v dd? = ?.?v v ss? + 0.? v dd? C 0.5 v t rt comparator response time v dd? = ?.? v; inp?t overdrive = 10mv 1 s sr slew rate v dd? = ?.? v; o?tp?t capacitor load c l =100pf 1.6 v/s note: g?aranteed by desi?n? not tested in prod?ction. gptm/mctm characteristics table 17. gptm/mctm characteristics symbol parameter conditions min typ max unit f tm timer clock so ?rce for gptm and mctm 7? mhz t res timer resol ?tion time 1 f tm f ext external si?nal freq?ency on channel 1 ~ 4 1/? f tm res timer resol ?tion 16 bits
rev. 1.00 ?6 of 45 ????st 1?? ?01? ??-bit ?rm cortex?-m? mcu ht??f1755/ht??f1765/ht??f?755 electrical characteristics i 2 c characteristics table 18. i 2 c characteristics symbol parameter conditions min typ max unit f scl scl clock freq ?ency 400 khz t scl(h) scl clock hi ?h time 600 ns t scl(l) scl clock low time 1?00 ns t f ?ll scl and sd ? fall time ?00 ns t rise scl and sd ? rise time ?00 ns t su(st ?) st ? rt condition set?p time 600 ns t h(st ?) st ? rt condition hold time 600 ns t su(sd?) sd? data set?p time 100 ns t h(sd?) sd? data hold time 0 ns t su(sto) stop condition set ?p time 600 ns t su(sta) t h(sta) t fall t scl(l) t rise t scl(h) t h(sda) t su(sda) t su(sto) scl sda figure 8. i 2 c timing diagrams
rev. 1.00 ?7 of 45 ????st 1?? ?01? ??-bit ?rm cortex?-m? mcu ht??f1755/ht??f1765/ht??f?755 electrical characteristics electrical characteristics spi characteristics table 19. spi characteristics symbol parameter conditions min typ max unit f sck sck clock freq?ency f pclk /4 mhz t sck(h) sck clock hi?h time f pclk /8 ns t sck(l) sck clock low time f pclk /8 ns spi master mode t v(mo) data o?tp?t valid time 5 ns t h(mo) data o?tp?t hold time ? ns t su(mi) data inp?t set?p time 5 ns t h(mi) data inp?t hold time 5 ns spi slave mode t su(sel) sel enable set ?p time 4 t pclk ns t h(sel) sel enable hold time ? t pclk ns t ?(so) data o?tp?t access time ? t pclk ns t dis(so) data o?tp?t disable time 10 ns t v(so) data o?tp?t valid time ?5 ns t h(so) data o?tp?t hold time 15 ns t su(si) data inp?t set?p time 5 ns t h(si) data inp?t hold time 4 ns sck (cpol = 0) sck (cpol = 1) mosi miso mosi miso t sck(h) t sck(l) t sck data valid data valid data valid data valid data valid data valid data valid data valid t v(mo) cpha = 0 cpha = 1 t h(mo) t h(mi) t su(mi) t v(mo) t h(mo) t su(mi) t h(mi) data valid data valid data valid data valid figure 9. spi timing diagrams C spi master mode
rev. 1.00 ?8 of 45 ????st 1?? ?01? ??-bit ?rm cortex?-m? mcu ht??f1755/ht??f1765/ht??f?755 electrical characteristics sck (cpol=0) sck (cpol=1) mosi miso t sck(h) t sck(l) t sck msb/lsb out msb/lsb in t v(so) t h(so) t su(si) t h(si) sel lsb/msb out lsb/msb in t a(so) t su(sel) t dis(so) t h(sel) figure 10. spi timing diagrams C spi slave mode and cpha=1 csif characteristics table 20. csif characteristics symbol parameter conditions min typ max unit f mck csif_mck clock freq?ency o?tp?t ?6 mhz f pck csif_pck clock freq?ency inp?t ?4 mhz r f ?pb clock and csif_pck clock inp?t freq?ency ratio f pclk /f pck ?
rev. 1.00 ?9 of 45 ????st 1?? ?01? ??-bit ?rm cortex?-m? mcu ht??f1755/ht??f1765/ht??f?755 electrical characteristics electrical characteristics usb characteristics the usb interface is usb-if certifed C full speed. table 21. usb dc electrical characteristics symbol parameter conditions min typ max unit v dd usb operatin? volta?e ?.0 ?.6 v v di differential inp ?t sensitivity |usbdp-usbdm| 0.? v v cm common mode volta?e ran?e 0.8 ?.5 v v se sin?le-ended receiver threshold 0.8 ?.0 v v ol pad o?tp?t low volta?e r l of 1.5k to v dd 0 0.? v v oh pad o?tp?t hi?h volta?e ?.8 ?.6 v v crs differential o ?tp?t si?nal cross-point volta?e 1.? ?.0 v z drv driver o?tp?t resistance 10 c in transceiver pad capacitance ?0 pf notes: 1. g?aranteed by desi?n? not tested in prod?ction. 2. to be compliant with the usb 2.0 full-speed electrical specifcation, the usbdp pin should be pulled up with a 1.5k external resistor to a 3.0 to 3.6v voltage supply . 3. the usb f ? nctionality is ens? red down to ?.7v b?t not the f? ll usb electrical characteristics which will experience de?radation in the ?.7 to ?.0v v dd volta?e ran?e. 4. r l is the load connected to the usb driver usbdp.
rev. 1.00 40 of 45 ????st 1?? ?01? ??-bit ?rm cortex?-m? mcu ht??f1755/ht??f1765/ht??f?755 electrical characteristics t r t f 90% 90% 10% 10% fall time rise time v crs figure 11. usb signal rise time and fall time and cross-point voltage (v crs ) defnition table 22. usb ac electrical characteristics symbol parameter conditions min typ max unit t r rise time c l = 50pf 4 ?0 ns t f fall time c l = 50pf 4 ?0 ns t r/f rise time / fall time matchin? t r/f = t r / t f 90 110 %
rev. 1.00 41 of 45 ????st 1?? ?01? ??-bit ?rm cortex?-m? mcu ht??f1755/ht??f1765/ht??f?755 electrical characteristics package information 5 package information note that the package information provided here is for consultation purposes only. as this information may be updated at regular intervals users are reminded to consult the holtek website (http://www. holtek.com.tw/english/literature/package.pdf) for the latest version of the package information. 48-pin lqfp (7mm7mm) outline dimensions symbol dimensions in inch min. nom. max. ? 0.?50 D 0.?58 b 0.?7? D 0.?80 c 0.?50 D 0.?58 d 0.?7? D 0.?80 e D 0.0?0 D f D 0.008 D g 0.05? D 0.057 h D D 0.06? i D 0.004 j 0.018 D 0.0?0 k 0.004 D 0.008 0 D 7
rev. 1.00 4? of 45 ????st 1?? ?01? ??-bit ?rm cortex?-m? mcu ht??f1755/ht??f1765/ht??f?755 package information symbol dimensions in mm min. nom. max. ? 8.90 D 9.10 b 6.90 D 7.10 c 8.90 D 9.10 d 6.90 D 7.10 e D 0.50 D f D 0.?0 D g 1.?5 D 1.45 h D D 1.60 i 0.10 j 0.45 D 0.75 k 0.10 D 0.?0 0 D 7
rev. 1.00 4? of 45 ????st 1?? ?01? ??-bit ?rm cortex?-m? mcu ht??f1755/ht??f1765/ht??f?755 package information package information 64-pin lqfp (7mm7mm) outline dimensions symbol dimensions in inch min. nom. max. ? 0.?50 D 0.?58 b 0.?7? D 0.?80 c 0.?50 D 0.?58 d 0.?7? D 0.?80 e D 0.016 D f 0.005 D 0.009 g 0.05? D 0.057 h D D 0.06? i 0.00? D 0.006 j 0.018 D 0.0?0 k 0.004 D 0.008 0 D 7 symbol dimensions in mm min. nom. max. ? 8.90 D 9.10 b 6.90 D 7.10 c 8.90 D 9.10 d 6.90 D 7.10 e D 0.40 D f 0.1? D 0.?? g 1.?5 D 1.45 h D D 1.60 i 0.05 D 0.15 j 0.45 D 0.75 k 0.09 D 0.?0 0 D 7
rev. 1.00 44 of 45 ????st 1?? ?01? ??-bit ?rm cortex?-m? mcu ht??f1755/ht??f1765/ht??f?755 package information 100-pin lqfp (14mm14mm) outline dimensions symbol dimensions in inch min. nom. max. ? 0.6?6 D 0.6?4 b 0.547 D 0.555 c 0.6?6 D 0.6?4 d 0.547 D 0.555 e D 0.0?0 D f D 0.008 D g 0.05? D 0.057 h D D 0.06? i D 0.004 j 0.018 D 0.0?0 k 0.004 D 0.008 0 D 7 symbol dimensions in mm min. nom. max. ? 15.90 D 16.10 b 1?.90 D 14.10 c 15.90 D 16.10 d 1?.90 D 14.10 e D 0.50 D f D 0.?0 D g 1.?5 D 1.45 h D D 1.60 i D 0.10 j 0.45 D 0.75 k 0.10 D 0.?0 0 D 7
rev. 1.00 45 of 45 ????st 1?? ?01? ??-bit ?rm cortex?-m? mcu ht??f1755/ht??f1765/ht??f?755 package information package information holtek semiconductor inc. (headquarters) no.?? creation rd. ii? science park? hsinch?? taiwan tel: 886- ?-56?-1999 fax: 886-?-56? -1189 http://www.holtek.com.tw holtek semiconductor inc. (taipei sales offce) 4f-?? no. ?-?? y ?anq? st.? nankan? software park? taipei 115? taiwan tel: 886- ?-?655-7070 fax: 886-?-?655-7?7? fax: 886-?-?655-7?8? (international sales hotline) holtek semiconductor inc. (shenzhen sales offce) 5f ? unit ?? prod?ctivity b?ildin?? no.5 gaoxin m ?nd road? nanshan district? shenzhen? china 518057 tel: 86-755-8616-9908 ? 86-755-8616-9?08 fax: 86-755-8616-97?? holtek semiconductor (usa), inc. (north america sales offce) 467?9 fremont blvd.? fremont? c? 945?8? us? tel: 1-510- ?5?-9880 fax: 1-510-?5?-9885 http://www.holtek.com copyri?ht ? ?01? by holtek semiconductor inc. the information appearin ? in this data sheet is believed to be acc ? rate at the time of p? blication. however ? holtek assumes no responsibility arising from the use of the specifcations described. the applications mentioned herein are ?sed solely for the p?rpose of ill?stration and holtek makes no warranty or representation that s?ch applications will be suitable without further modifcation, nor recommends the use of its products for application that may present a risk to h?man life d?e to malf?nction or otherwise. holtek's prod?cts are not a?thorized for ?se as critical components in life s?pport devices or systems. holtek reserves the ri?ht to alter its prod?cts witho? t prior notifcation. for the most up-to-date information, please visit our web site at http://www.holtek.com.tw.

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